1. Field of the Invention
The present invention relates to a driving circuit for driving a plasma display unit, and more specifically, to a low loss driving circuit for driving a plasma display while minimizing circuit complexity.
2. Description of the Prior Art
Plasma display panels are thin panels that can display over a large screen without emitting harmful radiation. Therefore, they are rapidly gaining popularity in the new large-panel market. The working principle of a plasma display panel (PDP) is to excite electric charges in the plasma by charging the PDP with a high frequency alternating voltage. In the activating process, ultraviolet rays are emitted to bombard the phosphor on the tube wall for emitting light. The plasma display panel behaves like a capacitor. When two electrodes of the PDP are suddenly short-circuited or charged by the high voltage, an inrush current will be generated which will induce electo-magnetic interference and a great loss of energy. This is a problem which the driving circuit of the plasma display panel must rectify. In order to reduce the inrush current, the driving circuit of a traditional plasma display panel uses an inductor to resonate with the intrinsic capacitor of PDP to slow down charging and discharging cycles of the plasma display panel. However, such a driving circuit is usually very complicated and costly.
Please refer to FIG. 1. FIG. 1 is a circuit diagram of a prior art single-sided driving circuit 10 for driving a plasma display unit 14. The plasma display unit 14 is represented by an equivalent load capacitor C.sub.L. The single-sided driving circuit 10 comprises a two-directional switch 12, four transistors M1, M2, M5 and M6, two diodes D1 and D2, an inductor L, a high-capacity capacitor C1, and two DC power supplies V and V.sub.G. The two-directional switch 12 comprises two transistors M3, M4 and two zener diodes ZD1 and ZD2 for limiting voltages.
Please refer to FIG. 2. FIG. 2 shows a timing diagram of the single-sided driving circuit 10 in FIG. 1. Diagram A shows a potential of an input node A of the two-directional switch 12. Diagram B shows a potential of an output node B of the two-directional switch 12. Diagram C shows a potential of a gate of the transistor M1. Diagram D shows a potential of a gate of the transistor M2. Diagram E shows a potential of a gate of the transistor M5. Diagram F shows a potential of a gate of the transistor M6. Vo is a potential of an output port of the plasma display unit 14. Io is a current flowing through the plasma display unit 14. Since sources of the transistors M1 and M5 are connected to high voltages, the transistor M1 or M5 will be turned on if the gate of the transistor M1 or M5 is connected to a low voltage, and turned off if the gate is connected to a high voltage. Since sources of the transistors M2 and M6 are connected to ground, the transistor M2 or M6 will be turned on if the gate of the transistor M2 or M6 is connected to a high voltage, and turned off if the gate is connected to a low voltage. The following outlines the control procedure illustrated by the timing diagrams of FIG. 2:
step 1: before T1, the output Vo of the plasma display unit 14 is at 0V, the transistors M2, M6 are in an on state, and the transistors M1, M5 are in an off state;
step 2: in T1, the gate C of the transistor M1 is reversed to a low voltage 22 thereby switching on the transistor M1 and raising the potential of node A to V.sub.G to control operations of the two-directional switch 12, the potential of the output node B will thus rise to V/2, and the inductor L and plasma display unit 14 will then resonate causing the output potential Vo rise to V slowly;
step 3: in T2, the gate D of the transistor M2 is reversed to a high voltage 24 thereby switching on the transistor M2 and dropping the input node A to 0V to control the two-directional switch 12 which causes the potential of the output node B rising to V and maintains the output potential Vo at V; because a potential difference between a drain and source of the transistor M5 is fairly close 0V, the parasitic diode existed between the drain and source thus becomes switched on, and reversing the gate E of the transistor M5 to a low voltage 26 at this time switches on the transistor M5 at a zero crossing voltage;
step 4: in T3, the gate C of the transistor M1 is again reversed to a low voltage 28 thereby switching on the transistor M1 and raising the potential of the input node A to switch on the two-directional switch 12 thus reducing the potential of the output node B to V/2, the gate E of the transistor M5 is reversed to a high voltage to switch off the transistor M5, and the inductor L and the plasma display unit 14 will resonate to slowly discharge the load capacitor C.sub.L until the output potential Vo drops to 0V;
step 5: in T4, the gate D of the transistor M2 is reversed to a high voltage thereby switching on the transistor M2 and dropping the input node A to 0V to turn off the two-directional switch 12, the output potential Vo is then maintained at 0V, and the output node B is dropped to 0V; since a potential difference between a drain and source of the transistor M6 is approaching to 0V, the parasitic diode is turned on, and reversing the gate F of the transistor M6 to a high voltage 30 at this time causes the transistor M6 to be switched on at a zero crossing voltage;
step 6: repeat step 2 to step 5 to charge and discharge the plasma display unit 14 continuously.
Because the inductor L and load capacitor C.sub.L of the single-sided driving circuit 10 form a resonance circuit, energy stored therein is mutually exchangeable. However, in order to avoid energy loss over the transistors M5, M6 and to ensure a smooth change of the output potential Vo, the transistors M5 and M6 can only be switched after resonance is achieved, that is, when the output potential Vo reaches 0 or V. At this time, the transistors M5, M6 are switched on at a zero crossing voltage since the potential difference between the drain and source of each of the transistors M5, M6 is 0.
Please refer to FIG. 3. FIG. 3 is a circuit diagram of a prior art double-sided driving circuit 40 formed by two single-sided driving circuits 10 in FIG. 1. The double-sided driving circuit 40 comprises two single-sided driving circuits 10 electrically connected to the two ends of the plasma display unit 14. The two single-sided driving circuits 10 are used for sustaining an image signal through charging and discharging the plasma display unit 14 continuously by driving plasma inside the plasma display unit 14 back and forth. Each of the single-sided driving circuits 10 comprises a two-directional switch 42 formed by the two-directional switch 12, transistors M1, M2, and DC power supply V.sub.G shown in FIG. 1, and switches Qa and Qb formed by the transistors M5 and M6. Because the double-sided driving circuit 40 uses many complicated components such as high-capacity capacitors C1, it is difficult and costly to control the driving circuit 40.